적응루프필터를 사용한 낮은 지터특성의 전하펌프PLL 클록발생기

• 영문명: A Low-Jitter CPPLL Clock Generator using Adaptive Loop Filter
• 발행기관: 한국산업기술융합학회(구. 산업기술교육훈련학회)
• 저자명: 이정기(Jung-Ki Lee)
• 간행물 정보: 『산업기술연구논문지』산업기술교육훈련논문지 제16권 4호, 271~280쪽, 전체 10쪽
• 주제분류: 공학 > 공학일반
• 파일형태: PDF
• 발행일자: 2011.12.30

영문 초록

This paper describes that the timing jitter is affected by changes of the scale factor N of a CPPLL(Charge-Pump Phase-Locked Loops) clock generator. The noise due to VCO(Voltage Controled Oscillator) is considered mainly, then the closed-form equations are derived from CPPLL output timing jitter related to parameters of a second-order CPPLL that simplified a third-order CPPLL. Verifying the performance, the variation of damping factor ？？ and natural frequency ？？ when the scale factor N is changed is estimated into Matlab analysis, the CPPLL clock generator that has digitally tunable bandwidth is integrated with CMOS technology. The proposed architecture shows that it maintains the output timing jitter around the 1% per half-period although the scale factor N is changed. The output timing jitter of the CPPLL clock generator using the adaptive loop filter is improved to the maximum 47% compared with a typical CPPLL clock generator when the scale factor N is changed.

목차

Ⅰ. 서 론

Ⅱ. HDTV 비디오신호 인터페이스 및 CPPLL의 동작원리

Ⅲ. 적응 루프 필터를 사용한 CPPLL 클록 발생기 설계

Ⅴ. 결 론

키워드

Charge-Pump Phase-Locked Loops(전하펌프 PLL) Clock Generator(클록발생기) Clock and Data Recovery(클록 데이터 복원회로) Adaptive Loop Filter(적응루프필터) Damping Rate(제동비) Output Timing Jitter(출력타이밍지터)