CMOS 공정에서 안테나 효과를 최소로 하기위한 레이아웃 방법에 관한 고찰

• 영문명: The Study of Physical Layout Methods for Reducing Antenna Effect in CMOS Process
• 발행기관: 한국산업기술융합학회(구. 산업기술교육훈련학회)
• 저자명: 이종진(Jong Jin Lee)
• 간행물 정보: 『산업기술연구논문지』산업기술교육훈련논문지 제15권 4호, 1~7쪽, 전체 7쪽
• 주제분류: 공학 > 공학일반
• 파일형태: PDF
• 발행일자: 2010.12.30

영문 초록

The antenna effect is that electromagnetic waves induce the strong accumulated charges in the interconnected metals connected to poly silicon gate of MOSFET during plasma processing of wafer and the accumulated charges break down gate oxide. A techniques can be utilized to minimize the antenna effect is the predicting of the occurrences of antennas by using layout and design verification software programs. Then by adjusting the physical layout of the inter-connects, the antenna effect can be reduced to an acceptable level. In addition, processing steps utilizing plasma can be optimized to reduce the build-up of charges on any antennas that do exist on devices. In this paper, several techniques of physical layout is studied and proposed new methode of physical layout to reduce antenna effect.

목차

ABSTRACT

Ⅰ. 서론

Ⅱ. 안테나 효과 및 고찰방법

Ⅲ. 레이아웃 및 특성고찰하기

Ⅳ. 결론

참고문헌

키워드

안테나효과 MOS형 전계효과트랜지스터 플라즈마공정 반도체 배치설계 Antenna Effect MOSFET Plasma Processing Physical Layout