듀얼-타입 전류 셀 매트릭스구조에서 CMOS D/A변환기의 설계

• 영문명: A Design of CMOS Digital to Analog Converter in Dual-Type Current Cell Matrix Architecture
• 발행기관: 한국산업기술융합학회(구. 산업기술교육훈련학회)
• 저자명: 권용복(Yong-Bok Kueon)
• 간행물 정보: 『산업기술연구논문지』산업기술교육훈련논문지 제17권 4호, 9~17쪽, 전체 9쪽
• 주제분류: 공학 > 공학일반
• 파일형태: PDF
• 발행일자: 2012.12.30

영문 초록

This paper describes a 3.3(V) 8 bit CMOS digital to analog converter (DAC) in dual-type current cell matrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric dual-type current cell matrix architecture allows the designed DAC to reduce not only a complexity of decoding logics, but also a number of wide swing cascade current mirrors. The designed DAC with an active chip area of 0.8(mm2)is fabricated by a 0.8(？？) CMOS n-well standard analog process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are 6(ns), 15(ns) and a less than ±0.8 ±？？0.75 LSB, respectively. The designed DAC is fully operational for the power supply down to 2.2(V), such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3(V) is measured to be 34.5(㎽).

목차

Ⅰ. 서 론

Ⅱ. 본 론

Ⅲ. 실험결과 및 고찰

Ⅳ. 결 론

키워드

Least Significant Bit(하위비트) Most Significant Bit(상위비트) Digital-To-Analog Converter(D/A변환기)