Critical Cleaning Requirements for Back End Wafer Bumping Processes

• 영문명: Critical Cleaning Requirements for Back End Wafer Bumping Processes
• 발행기관: 한국마이크로전자및패키징학회
• 간행물 정보: 『마이크로전자 및 패키징학회지』제7권 제1호, 51~59쪽, 전체 9쪽
• 주제분류: 공학 > 산업공학
• 파일형태: PDF
• 발행일자: 2000.03.31

영문 초록

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

목차

Introduction

Wafer Bumping Critical Cleaning Requirement

Masks used to Expose Bond Pads for Bump Sites

Molybdenum Mask

Photoresist Mask

New Aprotic Solvent Semi-Aqueous Technology

Conclusion

References