고속 프로그램 알고리즘을 이용한 스마트 칩 설계

• 영문명: A Smart Chip Design using High Speed Program Algorithm
• 발행기관: 한국산업기술융합학회(구. 산업기술교육훈련학회)
• 저자명: 김종습(Jong-Seub Kim)
• 간행물 정보: 『산업기술연구논문지』산업기술교육훈련논문지 제17권 1호, 65~74쪽, 전체 10쪽
• 주제분류: 공학 > 공학일반
• 파일형태: PDF
• 발행일자: 2012.03.30

영문 초록

Bulk of toner residual quantity detection return trip conglutinated in toner of using printer current is comparative big state by using PCB substrate, therefore is incongruent to use in light weight print miniaturized more. Return trip this development miniaturizes such as this by doing one chip competitive product develop Chip has to be conglutinated compulsorily in toner used to printer announced since 2005 years. Therefore, demand of chip to be used in forward revival market may be thriving. Production of revival toner is impossible by chip conglutinated to printer to meaning that manage information of toner cut ridge that universal laser printer makers are used in printer and do customer service. This research institute develops chip conglutinated compulsorily to produce revival toner.

목차

Ⅰ. 서 론

Ⅱ. 회로설계 및 Layout 설계

Ⅲ. 결 론

키워드

EEPROM Cell(메모리) Charge Pump(충전펌프) High Voltage Regulator(고전압 조정기) Ring Oscillator(링 발진기)