3-Lavel PLA實現 및 EXCLUSIVE - OR셀 어레이 LAYOUT 硏究

• 영문명: “The Reseach On 3-Level PLA Implementation And Layout of Exclusive-OR Cell Array”
• 발행기관: 호서대학교 사회과학연구소
• 저자명: 文大哲(Dai Tdiue Moon)
• 간행물 정보: 『사회과학연구』제4집 제1호, 419~431쪽, 전체 13쪽
• 주제분류: 사회과학 > 행정학
• 파일형태: PDF
• 발행일자: 1985.12.31

영문 초록

In this paper deal with the theoretical method of 3-level PLA and design of exclusive-OR array cell for 3-level PLA. Most PLA have constraints on minimal chip area and minimal input lines, thus the reduction of the number of product term in a sum of products expression is important in conventional random logic circuits. Also, this paper deals with lay out of Exclusive-ORArray using CHISEL language.

목차

ABSTRACT

Ⅰ. 序論

Ⅱ. 3LEVEL PLA 實現

Ⅲ. Exclusive-OR Array Cell 設計 및 Layout

Ⅳ. 結論

參考文獻