3D 적층 IC를 위한 웨이퍼 레벨 본딩 기술

• 영문명: Wafer Level Bonding Technology for 3D Stacked IC
• 발행기관: 한국마이크로전자및패키징학회
• 간행물 정보: 『마이크로전자 및 패키징학회지』제20권 제1호, 7~13쪽, 전체 7쪽
• 주제분류: 공학 > 산업공학
• 파일형태: PDF
• 발행일자: 2013.03.31

영문 초록

3D stacked IC is one of the promising candidates which can keep Moore's law valid for next decades. IC can be stacked through various bonding technologies and they were reviewed in this report, for example, wafer direct bonding and atomic diffusion bonding, etc. As an effort to reduce the high temperature and pressure which were required for high bonding strength in conventional Cu-Cu thermo-compression bonding, surface activated bonding, solid liquid inter-diffusion and direct bonding interface technologies are actively being developed.

목차

1. 서론

2. 본딩 기술

3. Hybrid bonding

4. Wafer level Cu-Cu thermo-compression bonding

감사의 글

참고문헌

키워드

3D IC wafer level stacking thermo-compression bonding