Wafer-to-Wafer Integration을 위한 생산수율 챌린지에 대한 연구

• 영문명: Manufacturing yield challenges for wafer-to-wafer integration
• 발행기관: 한국마이크로전자및패키징학회
• 간행물 정보: 『마이크로전자 및 패키징학회지』제20권 제1호, 1~5쪽, 전체 5쪽
• 주제분류: 공학 > 산업공학
• 파일형태: PDF
• 발행일자: 2013.03.31

영문 초록

Wafer-to-Wafer (W2W) integration technology is an emerging technology promising many benefits, such as reduced size, improved performance, reduced power, lower cost, and divergent integration. As the maturity of W2W technology progresses, new applications will become more viable. However, at present the cost for W2W integration is still very high and both manufacturing yield and reliability issues have not been resolved yet for high volume manufacturing (HVM). Especially for WTW integration resolving compound yield issue can be a key factor for HVM. To have the full benefits of WTW integration technology more than simple wafer stacking technologies are necessary. In this paper, the manufacturing yield for W2W integration is described and the challenges of WTW integration will be discussed.

목차

1. Introduction

2. Yield Improvement Methods

3. Summary

Acknowledgement

References

키워드

3D stacked IC Yield TSV 3D Integration Wafer-to-Wafer