A Study on the Correlation Between Board Level Drop Test Experiment and Simulation

• 발행기관: 한국마이크로전자및패키징학회
• 간행물 정보: 『마이크로전자 및 패키징학회지』제18권 제2호, 35~41쪽, 전체 7쪽
• 주제분류: 공학 > 산업공학
• 파일형태: PDF
• 발행일자: 2011.06.30

영문 초록

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

목차

1. Introduction

2. Theoretical Analysis

3. Drop Test Experiment

4. Drop Test Simulation

5. Correlation of Experiment & Simulation Results

6. Conclusions

References

키워드

Board level drop test Package drop test Drop test