Fabrication and Challenges of Cu-to-Cu Wafer Bonding

• 발행기관: 한국마이크로전자및패키징학회
• 간행물 정보: 『마이크로전자 및 패키징학회지』제19권 제2호, 29~33쪽, 전체 5쪽
• 주제분류: 공학 > 산업공학
• 파일형태: PDF
• 발행일자: 2012.06.30

영문 초록

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

목차

1. Introduction

2. Experimental Procedure

3. Results and Discussion

4. Conclusions

Acknowledgments

References

키워드

Wafer bonding Misalignment Cu bonding CMP