Cu-SiO2 하이브리드 본딩

• 영문명: Cu-SiO2 Hybrid Bonding
• 발행기관: 한국마이크로전자및패키징학회
• 간행물 정보: 『마이크로전자 및 패키징학회지』제27권 제1호, 17~24쪽, 전체 8쪽
• 주제분류: 공학 > 산업공학
• 파일형태: PDF
• 발행일자: 2020.03.31

영문 초록

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO2 hybrid bonding.

목차

1. 서론

2. 구리 본딩의 종류

3. Cu-SiO2 하이브리드 본딩 Process Flow

4. 저온 Cu-SiO2 하이브리드 본딩

5. 결론

감사의 글

References

키워드

Copper Bonding Hybrid Bonding Interconnect 3D Packaging