새로운 지수연산 블록 구조를 갖는 고속 저전력 베다 곱셈기의 설계

• 영문명: A Vedic Multiplier with A Novel Architecture of Exponent Block for High-Speed and Low-Power
• 발행기관: 한국산업기술융합학회(구. 산업기술교육훈련학회)
• 저자명: 류기주(Gi-Ju Ryu) 서해준(Hae-Jun Seo)
• 간행물 정보: 『산업기술연구논문지』산업기술교육훈련논문지 제20권 1호, 9~14쪽, 전체 6쪽
• 주제분류: 공학 > 공학일반
• 파일형태: PDF
• 발행일자: 2015.03.30

영문 초록

Vedic Mathematics is based on 16 formulas with the purpose of simplification of lengthy and complex mathematics. NND(Nikhilam Navatashcaramam Dashatah) sutra is most efficient algorithm, giving minimum delay for multiplication of all types numbers. In this paper modified vedic multiply algorithm has been devised at architecture level to improve the speed and power of the multiplier. The main idea of the improvement is based on using priority encoder in residue exponent determinant unit. The proposed multiplier results in 45% of speed-up and 42% of reduction of power consumption. This multiplier is composed of Xilinx FPGA and designed RTL(Register Transfer Level) using Xilinx ISE software.

목차

Ⅰ. 서 론

Ⅱ. 실 험

Ⅲ. 실험결과 및 고찰

Ⅳ. 결 론

키워드

Vedic Multiplier(베다 곱셈기) Encoder(인코더) Shifter(쉬프터) Radix(기수) Exponent(지수)